Job Description

Our partner is looking for a Low Power Verification Lead to ensure low power intent is implemented and verified correctly across the full design flow.

The role focuses on VCLP signoff, UPF development, hierarchical low power verification and convergence between RTL, synthesis and physical design.

Location: Barcelona, Spain, Hybrid
Level: Senior

Responsibilities

• Develop and maintain UPF for hierarchical designs

• Validate low power architecture and intent across multiple power domains

• Debug VCLP failures related to clock gating, retention, isolation and level shifters

• Ensure UPF convergence across synthesis, place and route, and ECO cycles

• Work closely with RTL, Synthesis, DFT and Physical Design teams

• Resolve low power issues across implementation stages

• Develop automation scripts for VCLP signoff

• Improve low power verification methodology and scalability

Requirements

• 7+ years of low power verification experience

• Strong hands on experience with VCLP

• Strong knowledge of UPF

• Hierarchical low power verification experience

• Understanding of retention, isolation, level shifters and clock gating

• Experience with synthesis, netlist optimization and equivalence debugging

• Tcl, Python or Perl scripting

• Bachelor or Master degree in Electrical Engineering, Electronics or related field

Optional / Desired

• RISC V experience

• DFT and scan interaction with UPF

• STA interaction with low power intent

• Physical Design interaction with UPF

• Experience improving low power signoff methodology

What’s in it for you?

• Flexible working hours

• Hybrid model, 4 days office, 1 day from home

• 1 week per year working from anywhere

• 25 days annual leave plus December 24 and 31

• Monthly food allowance

• Private medical insurance

• Relocation bonus

• Housing search support

• Visa support if required

• Family relocation support

• Virtual shares

• Language classes

• Tax incentive, subject to eligibility