Our client is expanding their Physical Design organization and is looking for Mid and Lead Physical Verification Engineers to support advanced semiconductor programs at cutting edge technology nodes.

In this role, you will be responsible for ensuring Physical Verification signoff quality across complex SoC designs. You will work closely with implementation, STA and layout teams to achieve clean tape out results and support advanced node production readiness.

Location: Barcelona, Spain - Hybrid

Responsibilities:

As a Mid / Senior Physical Verification Engineer, your broad responsibilities will include but are not limited to:

• Drive Physical Verification signoff including DRC, LVS, PERC and Antenna checks at advanced process nodes

• Collaborate with Place and Route, STA and Layout teams to resolve PV violations efficiently

• Develop, maintain and optimize PV methodologies and runsets for low nanometer nodes

• Communicate with foundries to align on rule decks and signoff criteria

• Support tape out readiness by ensuring PV closure with clean signoff results

• Automate flows and scripts to improve PV productivity and turnaround time

Additional Responsibilities for Lead Physical Verification Engineers Only:

• Own overall PV strategy and signoff readiness for assigned blocks or full chip

• Drive methodology improvements across the PV team

• Coordinate PV planning and milestone tracking with implementation leads

• Mentor and guide junior and mid level PV engineers

• Act as escalation point for complex PV issues

Requirements:

• Bachelor or Master degree in Electrical Engineering, Computer Engineering or related field

• Solid experience in Physical Design with strong focus on Physical Verification

• Hands on expertise with PV tools such as Mentor Calibre or Synopsys ICV

• Strong understanding of low nanometer process design rules and foundry requirements

• Experience supporting advanced node tape outs such as 7nm, 5nm, 3nm or below

• Strong scripting skills using TCL, Python or Shell

• Strong analytical and problem solving skills

• English level C1 or higher

Additional Requirements for Lead Physical Verification Engineers Only:

• Proven experience owning PV closure for complex SoC or large subsystems

• Demonstrated ability to lead technical efforts and coordinate cross functional teams

• Experience driving PV methodology standardization across projects

What’s in it for you?

Our client offers an exciting, challenging role in a collaborative, dynamic environment. The right person will find many career growth opportunities in their company, whether you want to advance your technical skills or aspire to leadership in the future.

Benefits:

• Flexible working hours ( You can work between 7 AM and 7 PM )

• Hybrid model, one day remote per week

• One week per year work from anywhere

• 25 days annual leave plus additional December 24 and 31

• Private medical insurance

• Relocation package including flight, visa support + first month accommodation

• Relocation support for family

• Virtual shares

• Spanish language classes